How to make a mobile Logic Analyzer February 13, 2008Posted by Florian in kernel concepts, Linux, Maemo, OpenEmbedded, Source.
Tags: Java, Logic Analyzer, mobile, N810, Neo1973, Open Source
Making a useful mobile Logic Analyzer is quite a challenge, but the basic needs are there. sump.org has a nice VHDL design and Java software for a 32 channel Logic Analyzer
based on a Xilinx Spartan FPGA. The whole design is GPL licensed. The current VHDL implementation is available for several Xilinx FPGA evaluation boards and uses a serial port for communication with a device (usually a PC) running the GUI software. The FPGA board takes care about sampling and buffering of the sample data before it is transferred to the controlling device.
Robert Schuster of tarent did a great job to get the Java software running on a Nokia N800 and on the Neo1973.
It was not too complicated to make the VHDL part work on an inexpensive Spartan-3E eval board. This hardware of course does not really fit the needs for two reasons: First it is too big to accompany a mobile consumer device such as a N810 or the Neo 1973. Second it does not support other input signal levels than 3.3V which is a real showstopper. A better hardware design that fits the needs based on a small FPGA industry module, a battery and some line drivers would be easy to do… but that’s something for a new story later :-) Before that I need to get a serial connection from a N810 to the board and check how the software performs on this device…
The board I used for my test was a Xilinx Spartan-3E Starter Kit.Ther is quite some room for improvement since a a major share of the FPGAs blocks are unused and it does not yet make much of use of all the nice features on the board such as external RAM, flash, display and USB.
Additional screenshots can be found at http://scap.linuxtogo.org.